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DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 1 version: DM9131-ds-f01 april 7, 2000 general description the DM9131 is a physic al-layer, single-chip, low- power transceiver for 100base-tx and 10base-t operations. on the media side, it provides a direct interface either to unshiel ded twis ted pair cable 5 (utp5) for 100base-tx fast ethernet, or utp5/utp3 cable for 10base-t ethernet, and it also provides pecl interface to connect the exter nal fiber optical transceiver. through the media independent interface (mii), the DM9131 connects to the medium access control (mac) layer, ensuring a high inter- operab ility am ong products from different vendors. the DM9131 uses a low-power and high-performance cmos process. it contains the entire physical layer functions of 100base-tx as defined by ieee 802.3u, including the physical coding sublayer (pcs), physical medium attachment (pma), twisted pair physical medium dependent sublayer (tp-pmd), 10base-tx encoder/decoder (enc/dec), and twisted pair media access unit (tpmau). the DM9131 provi des a st rong support for the auto- negotiation function u tiliz ing automatic media speed and protocol selection. furthermore, due to the built- in wave-shaping filter, the DM9131 needs no external filter to transport signals to the media in 100m or 10m ethernet operation. block diagram mii management control biasing/ power block clock circuit block 100base-tx transceiver 100base-fx pecl interface led driver mii interface mii register 100base- tx pcs 10base-t tx/rx module auto-negotiation
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 2 final version: DM9131-ds-f01 april 7, 2000 table of contents general description ................................................1 block diagram ........................................................1 features .................................................................3 pin configuration: dm9101e lqfp ........................4 pin description .......................................................5 normal mii interface, 21 pins...............................5 media interface, 5 pins ........................................6 led interface, 5 pins ...........................................6 mode, 11 pins ......................................................7 bias and clock, 6 pins .........................................7 power and others, 52 pins ...................................8 functional description transmit section .................................................9 100base-tx operation ........................................9 mii serial management interface .........................9 management interface ? read frame structure ..9 management interface ? write frame structure .9 mii register description........................................10 - key to default ...................................................10 basic mode control register (bmcr) - 00 ............11 basic mode status register (bmsr) - 01 .............12 phy id identifier register #1 (phyidr1) - 02 ......13 phy id identifier register #2 (phyidr2) - 03 ......13 auto-negotiation advertisement register (anar) - 04.......................................................................14 auto-negotiation link partner ab ility register (anlpar) - 05......................................................15 auto-negotiation expansion register (aner) - 06.......................................................................16 davicom specified configuration register (dscr) - 16.......................................................................16 davicom specified configuration and status register (dscsr) - 17 .........................................18 10base-t configuration / status (10btcsr) - 18 .19 davicom specified interrupt register - 21.......... 20 davicom specified receive error counter register (recr) - 22 ......................................................... 20 davicom specified disconnect counter register (discr) - 23 ........................................................ 20 absolute maximum ratings.................................. 21 operating conditions ......................................... 21 dc electrical characteristics ................................ 22 ac electrical characteristics & timing waveforms ............................................................................ 22 tp interface ...................................................... 22 oscillator/crystal timing ................................... 22 mdc/mdio timing............................................ 23 mdio timing when output by sta ............... 23 mdio timing when output by DM9131 ......... 23 mii 100base-tx transmit timing parameters... 24 mii 100base-tx transmit timing diagram ........ 24 mii 100base-tx receive timing parameters .... 24 mii 100base-tx receive timing diagram ......... 25 mii 10base-t nibble transmit timing parameters ......................................................................... 25 mii 10base-t nibble transmit timing diagram . 25 mii 10base-t receive nibble timing parameters ......................................................................... 26 mii-10base-t receive nibble timing diagram .. 26 auto-negotiation and fast link pulse timing parameters ....................................................... 26 auto-negotiation and fast link pulse timing diagram ............................................................ 27 package information ............................................ 28 ordering information ............................................ 29 disclaimer ............................................................ 29 company overview .............................................. 29 product ................................................................ 29 warning ............................................................... 29 contact windows ................................................. 29
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 3 version: DM9131-ds-f01 april 7, 2000
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 4 final version: DM9131-ds-f01 april 7, 2000 features fully compliant w ith i eee 802.3u 10base-t/100base- tx compliant with ansi x3t12 tp-pmd 1995 standard support auto-negotiation function, compliant to ieee 802.3u single-chip fully integrated physical layer interface - directly to magnetic integrated 10base-t and 100base-tx transceiver on-chip filtering, no need for exter nal filters selectable repeater or node mode far end fault signaling option in fx mode selectable twisted-pair or fiber mode output selectable full-duplex or half-duplex operation mii management interface with maskable interrupts output capab ility provides loopback mode for easy system diagnostics status led output provides link & activity, speed10/100 and full-duplex/c ollision led low-power, single-supply 3.3v cmos technology compatible with 3.3v and 5.0v tolerant i/o 100-pin lqfp
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 5 version: DM9131-ds-f01 april 7, 2000 pin configuration 11 DM9131 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 35 34 33 32 31 30 29 28 27 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 76 77 78 79 80 81 82 83 84 nc nc reset# nc dvcc rxer/rxd[4]/rptr rxdv col nc rxen crs/bp4b5b rxclk mdintr# nc rxd[0] rxd[1] rxd[2] rxd[3] nc dvcc mdio mdc nc nc 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 nc nc dgnd nc txclk rmii nc dvcc txen txd[0] nc txd[1] txd[2] txer/txd[4] nc dgnd txd[3] linkled link&actled# fdx/colled# trfled# dvcc speedled# pwrdwn nc nc testmode phyadr4 phyadr3 phyadr2 phyadr1 phyadr0 nc dgnd nc xt2 oscsel oscin/ref_clk nc dvcc nc xt1 nc dgnd agnd nc sd nc avcc nc nc bgresg bgres nc avcc rx+/fxrd+ rx-/fxrd- avcc agnd agnd agnd agnd tx+/fxtd+ tx-/fxtd- nc avcc pllvcc nc pllgnd dgnd nc opmode0 opmode1 opmode2 nc 26 36 56 nc
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 6 final version: DM9131-ds-f01 april 7, 2000 pin description i : input, o : output, li : latch input when power-up/reset, z : tri-state output normal mii interface, 21 pins pin no. pin name i/o description 38 txer/txd[4] i transmit error/the fifth txd data bit in 100mbps m ode, when the signal actives high and txen actives, the halt symbol is substituted for the actual data nibble. in 10mbps, the input is ignored. in bypass mode (bypass bp4b5b), txer becomes the txd[4] pin, the fifth txd data bit of the 5b symbol. 42,41,40,39 txd[0:3] i transmit data 4 bits nibble data input (synchronous to the txclk) when in 10/ 100mbps nibble mode. in 10mbps serial mode, the txd[0] pin is used as the serial data input pin, and txd[1:3] are ignored. 43 txen i transmit enable active high to indi cate the presence of valid nibble data on the txd[0:3] for both 100mbps and 10mbps nibble mode. in 10mbps se rial mode, active high indicates the presence of valid 10mbps data on txd[0]. 47 txclk o,z transmit clock the transmitting clock provides the timing reference for the transfer of the txen, txd, and txer. txclk is provided by the phy. 25mhz in 100mbps nibble mode, 2.5mhz in 10mbps nibble mode, 10mhz in 10mbps se rial mode. 53 mdc i management data clock synchronous clock for the mdio management data. this clock is provided by managem ent entity, and it is up to 2.5mhz 54 mdio i/o management data i/o bi-directional management data that may be provided by the station management entity or the phy. 61,60,59,58 rxd[0:3] o,z receive data output 4 bits nibble data output (synchronous to rxclk) when in 10/100mbps nibble mode. in 10mbps se rial mode, the rxd[0] pin is used as the serial data ou tput pin, and the rxd[1:3] are ignored. 63 mdintr# o status interrupt output: asserted low whenever there is status change.(link, speed, duplex) 64 rxclk o,z receive clock, the received clock provides the timing reference for the transfer of the rxdv, rxd, and rxer. rxclk is provided by phy. the phy may recover the rxclk reference from the received data or it may derive the rxclk reference from a nominal clock. 25mhz in 100mbps nibble mode, 2.5mhz in 10mbps nibble mode, 10mhz in 10mbps se rial mode. 65 crs/( bp4b5b ) o,z /li carrier sense detect/bypass 4b/5b encoder/decoder asserted high to indi cate the presence of carrier dues to receive or
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 7 version: DM9131-ds-f01 april 7, 2000 transmit activities in 10base-t or 100base-tx half-duplex mode. in repeater mode or full-duplex mode, this signal is asserted high to indicate the presence of carrier due only to the receive activity. this pin is also used as bypass 4b/5b encoder/dec oder.(power up reset latch input) 0 = normal operation 1 = bypass 4b5b 66 col o,z collision detection asserted high to indi cate that detection of the co llision condi tions in 10mbps and 100mbps half-duplex mode. in full-duplex mode, t his signal is always logical 0. 67 rxdv o,z receive data valid asserted high to indi cate that the valid data is present on the rxd[0:3]. 68 rxer/rxd[4] /(rptr/node) o,z /li receive data error/the fifth rxd data bit of the 5b symbol asserted high to indi cate that an invalid symbol has been detected. in decoder bypass mode (bypass bp4b5b), rxer becomes rxd[4], the fifth rxd data bit of the 5b symbol. these pins are also used to select repeater or n ode m ode. (power up reset latch input). 0 = node mode (default) 1 = repeater mode 69 rxen i receive enable : active high enable for receive signals rx d[0:3], rxclk, rxdv and rxclk. a low on this input tri-states these output pins. for normal operation in a node app lication, this pin should be pulled high. in repeater application, this pin may be connected to a repeater controller. 73 reset# i reset active low input that initializes the DM9131. media interface, 5 pins pin no. pin name i/o description 7,8 rx+/fxrd+ rx-/fxrd- i differential receive pair/pecl receive pair differential data is received from the media. differential pseudo ecl signal is received from the media in fiber m ode. 13,14 tx+/fxtd+ tx-/fxtd- o differential transmit pair/pecl transmit pair differential data is transmitted to the media in tp mode. differential pseudo ecl signal transmits to the media in fiber mode. 97 sd i fiber-optic signal detect pecl signal which indicates whether or not the fiber-optic receive pair is receiving valid signal levels. led interface, 5 pins pin no. pin name i/o description 31 trfled# o traffic led active low. it flashes when the DM9131 is transmitting or receiving data. 32 fdxled /colled# o full-duplex led/collision led : active low. indicates full-duplex mode for 100mbps and 10mbps operation. it is changed to co llision led funct ion w hen bit 4 of r egister 16 is set to 1.
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 8 final version: DM9131-ds-f01 april 7, 2000 33 speedled# o speed led: driven low when operating in 100mbps and high w hen operating in 10mbps. when bit 6 of register 16 is set, it controls the speedled as 100base- tx sd signal output. for debug only. 34 link&act led# o link led & ac tivity led : active low to indicate good link for 10mbps and 100mbps oper ation. it is also a activity led function when transmit or receive data. 35 linkled o link led active high to indi cate good link for 10mbps and 100mbps operation mode, 11 pins pin no. pin name i/o description 22,23,24 opmode0~2 li opmode0~opmode2 : these pins are used to control the forced or advertised operating mode of the DM9131 according to the following table. the v alue is lat ched into the DM9131 registers at power-up/reset. op2 op1 op0 function 0 0 0 auto negotiat ion enable with all capabilities 0 0 1 manual select 100tx fdx 0 1 0 manual select 100tx hdx 0 1 1 manual select 10tx fdx 1 0 0 manual select 10tx hdx 1 0 1 manual select 100fx fdx 1 1 0 manual select 100fx hdx 1 1 1 dual speed 100/10 hdx 27 rmii i reduced mii enable: this pin is used to select normal mii or reduced mii. ?0?= normal mii, (default) ?1?= reduced mii. this pin always pull- low exc ept that DM9131 is used as r educed mii. 28 pwrdwn i power down control assert high to force DM9131 into power down mode. when in power down mode, most of the DM9131 circuit block?s power is truned off, only the mii management interface (mdc, mdio) logic is available (the phy should respond to management transactions and should not generate spurious signals on the mii)). to leave power down m ode, d m9131 need the hardware or software reset with the pwrdwn pin to low. 77 testmode i test mode control pin. 0 = normal operation 1 = enable test mode 82~78 phyadr[0:4] i phy address phy address sensing input pins.
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 9 version: DM9131-ds-f01 april 7, 2000 bias and clock, 6 pins pin no. pin name i/o description 2 bgresg p bandgap ground 3 bgres p bandgap voltage reference resistor 6.2k ohm 86 oscsel i oscillator or crystal selection. ?0? = crystal, ?1? = oscillator 87 oscin / ref_clk i oscillator i nput (25mhz) or reduced mii reference clock input (50mhz for reduced mii only). 91 xt2 o crystal output 92 xt1 i crystal input power and others, 52 pins pin no. pin name i/o description 5,6,16,99 avcc p analog power 9,10,11,12,95 agnd p analog ground 30,45,56,71, 89 dvcc p digital power 20,36,49,84 ,94 dgnd p digital ground 17 pllvcc p analog power 19 pllgnd p analog ground 1,4,15,18,21, 25,26,29,37, 44,46,48,50, 51,52,55,57, 62,70,72,74, 75,76,83,85, 88,90,93,96, 98,100 nc not connected.
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 10 final version: DM9131-ds-f01 april 7, 2000 functional description the DM9131 fast ethernet single-chip phy transceiver, provides the functionality as specified in ieee802.3, integrates the complete 100base-tx module and the complete 10base-t module. the DM9131 also provides a standard media independent interface (mii) to connect a media access controller and a network media. the DM9131 performs all pcs, pma, and tp-pmd sub-layer as defined by specification. transmit section the transmit section consists of the following blocks: - pcs transmit - clock generator - nrz to nrzi. mlt3 encoder and driver - manchester encoder - 10baset-tx filter and driver 100base-tx operation the 100base-tx transmitter receives 4 -bit nibble- data clocked in at 25mhz at the mii and outputs scrambled 5-bit encoded mlt-3 signal to the media at 100mbps. the on-chip clock circuit converts 25mhz clock into a 125mhz clock for internal use. mii serial management interface the serial management interface uses a si mple, two- wired serial interface to obtain and control the status of the physical layer thr ough an mii interface (mdc and mdio pins). the management data clock (mdc) is equipped with a max imum clock rate of 2.5mhz, while management data input /output (mdio) works as a bi-directional, open-drain pin shared by up to 32 devices. DM9131?s management functions correspond to mii specification for ieee 802.3u-1995 (clause 22) and the registers 0 through 6 with vendor-spe cific registers 11,15,16,17,18. in read/write operation, the management data frame is 64-bit long start with 32 conti guous logic one bits (preamble) synchronization clock cycles on mdc. the start of frame delimiter (sfd) is indi cated by a <01> pattern followed by the operation code (op):<10> indicates read operation and <01> indicates write operation. for read operat ion, a 2-bit turnaround (ta) f iling between r esistor address field and data field is provided for mdio to avoid contention. ?z? stands for high impedance state. following turnaround time, a 16-bit data is r ead from or written onto management registers. management interface - read frame structure 32 "1"s 0110a4a3a0r4r3r0 z 0 idle preamble sfd op code phy address register address turn around data idle read write mdc mdio read d15 d14 d1 d0 / / / / management interface - write frame structure 32 "1"s 0 1 1 0 a4 a3 a0 r4 r3 r0 1 0 d15 d14 d1 d0 idle preamble sfd op code phy address register address turn around data idle write mdc mdio write
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 11 version: DM9131-ds-f01 april 7, 2000 mii register description add name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 control reset loop back speed select auto-n enable power down isolate restart auto-n full duplex coll. test reserved 01 status t4 cap. tx fdx cap. tx hdx cap. 10 fdx cap. 10 hdx cap. reserved pream. supr. auto-n compl. remote fault auto-n cap. link status jabber detect extd cap. 02phyid100 00000 1 1000000 0 03 phyid2 1 0 1 1 1 0 model no. version no. 04 auto-neg. advertise next page flp rcv ack remote fault reserved fc adv t4 adv tx fdx adv tx hdx adv 10 fdx adv 10 hdx adv advertised protocol selector field 05 link part. ability lp next page lp ack lp rf reserved lp fc lp t4 lp tx fdx lp tx hdx lp 10 fdx lp 10 hdx link partner protocol selector field 06 auto-neg. expansion reserved pardet fault lp next pg able next pg able new pg rcv lp auton cap. 16 aux. config. bp 4b5b bp scr bp align bp_ad pok repeat mode tx/fx select fef enable rmii enable force 100lnk spdle d_ctl rsvd fdxle d_ctl reset st. mch pream. supr. sleep mode remote loopout 17 aux. conf/stat 100 fdx 100 hdx 10 fdx 10 hdx reserved phy addr [4:0] auto-n. monitor bit [3:0] 18 10t conf/stat rsvd lp enable hbe enable sque enable jab enable 10t serial reserved polarity reverse 21 mdintr intr pend rsvd rsvd rsvd fdx mask spd mask link mask intr mask rsvd rsvd rsvd fdx change spd change link change int enable intr status 22 rcv error counter receive error counter 23 disconnect counter reserved disconnect counter key to default in the register description that follows, the default column takes the form: , / where : 1 bit set to logic one 0 bit set to logic zero x no default value (pin#) value latched in from pin # at reset : ro = read only rw = read/write : sc = self clearing p = value permanently set ll = latching low lh = latching high
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 12 final version: DM9131-ds-f01 april 7, 2000 basic mode control register (bmcr) - 00 bit bit name default description 0.15 reset 0, rw/sc reset: 1=software reset 0=normal operation this bit sets the status and controls the phy registers to their default states. this bit, which is self-clearing, will k eep returning a value of one until the reset process is completed 0.14 loopback 0, rw loopb ack: loop-back control register 1 = loop-back enabled 0 = normal operation when in 100mbps operation m ode, sett ing this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appear at the mii receive outputs 0.13 speed selection 1, rw speed select: 1 = 100mbps 0 = 10mbps link speed may be selected either by this bit or by auto-negotiation. when auto- negotiation is enabled and bit 12 is set, this bit will return auto- negotiat ion selected media type. 0.12 auto- negotiation enable 1, rw auto-negotiation enable: 1 = auto-negotiation is enabled, bit 8 and 13 w ill be in auto- negotiation status 0.11 power down 0, rw power down: while in the power-down state, the phy should respond to management transactions. during the transition to power-down state and while in the power-down state, the phy should not generate spurious signals on the mii. 1=power down 0=normal operation 0.10 isolate 0,rw isolate: 1 = isolates the DM9131 from the mii with the exception of the serial management. (when this bit is asserted, the DM9131 does not respond to the txd[0:3], tx_en, and tx_er inputs, and it shall present a high i mpedance on its tx_clk, rx_clk, rx_dv, rx_er, rx[0:3], col and crs o utputs. when phy is i solated from the mii it shall respond to the management transactions) 0 = normal operation 0.9 restart auto- negotiation 0,rw/sc restart auto-negotiation: 1 = restart auto-negotiation. re-initiates the auto- negotiation process. when auto- negotiation is di sabled (bit 12 of this register cleared), this bit has no func tion and it s hould be cleared. this bit is self-clearing and it w ill keep returning a value of 1 until auto- negotiation is initiated by the dm 9131. the operation of the auto- negotiation process will not be affected by the managem ent entity that clears this bit 0 = normal operation
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 13 version: DM9131-ds-f01 april 7, 2000 0.8 duplex mode 1,rw duplex mode: 1 = full duplex operation. duplex selection is allowed when auto- negotiation is disabled (bit 12 of this register is cleared). with auto-negotiation enabled, this bit refle cts the duplex c apability selected by auto- negotiation 0 = normal operation 0.7 collision test 0,rw collision test: 1 = collision test enabled. when set, this bit w ill cause the col signal to be asserted in response to the assertion of tx_en 0 = normal operation 0.6-0.0 reserved 0,ro reserved: write as 0, ignore on read basic mode status register (bmsr) - 01 bit bit name default description 1.15 100base-t4 0,ro/p 100base-t4 capable: 1 = DM9131 is able to perform in 100 base-t4 mode 0 = DM9131 is not able to perform in 100 base-t4 mode 1.14 100base-tx full duplex 1,ro/p 100base-tx full duplex capable: 1 = DM9131 is able to perform 100base-tx in full duplex mode 0 = DM9131 is not able to perform 100base-tx in full duplex mode 1.13 100base-tx half duplex 1,ro/p 100base-tx half duplex capable: 1 = DM9131 is able to perform 100base-tx in half duplex mode 0 = DM9131 is not able to perform 100base-tx in half duplex mode 1.12 10base-t full duplex 1,ro/p 10base-t full duplex capable: 1 = DM9131 is able to perform 10base-t in full duplex mode 0 = DM9131 is not able to perform 10base-tx in full duplex mode 1.11 10base-t half duplex 1,ro/p 10base-t half duplex capable: 1 = DM9131 is able to perform 10base-t in half duplex mode 0 = DM9131 is not able to perform 10base-t in half duplex mode 1.10-1.7 reserved 0,ro reserved: write as 0, ignore on read 1.6 mf preamble suppression 0,ro mii frame preamble suppr ession: 1 = phy will accept m anagement f rames with preamble suppressed 0 = phy will not accept m anagement frames with preamble suppressed 1.5 auto- negotiation complete 0,ro auto-negotiation complete: 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 1.4 remote fault 0, ro/lh remote fault: 1 = remote fault condition detected (cleared on read or by a chip reset). fault criteria and detection met hod is dm 9131 implementation specific. this bit will set after the rf bit in the anlpar (bit 13, register address 05) is set 0 = no remote fault condition detected 1.3 auto- negotiation ability 1,ro/p auto configuration ability: 1 = DM9131 is able to perform auto- negotiation 0 = DM9131 is not able to perform auto- negotiation 1.2 link status 0,ro/ll link status:
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 14 final version: DM9131-ds-f01 april 7, 2000 1 = valid link is established (for either 10mbps or 100mbps operation) 0 = link is not established the link status bit is implemented with a latching function, so that the occurrence of a link failure c ondition causes the link status bit to be cleared and remain cleared until it is read via the m anagement interface 1.1 jabber detect 0, ro/lh jabber detect: 1 = jabber condition detected 0 = no jabber this bit is implemented with a latching function. jabber c onditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9131 reset. this bit works only in 10mbps mode 1.0 extended capab ility 1,ro/p extended capability: 1 = extended register capable 0 = basic register capable only phy id identifier register #1 (phyid1) - 02 the phy identifier registers #1 and #2 work together in a single identifier of the DM9131. the identifier consists of a concatenation of the organizationally uni que identifier (oui), a vendor's model number, and a model revision number. davicom semiconductor's i eee assigned oui is 00606e. bit bit name default description 2.15-2.0 oui_msb <0181h> oui most significant bits: this register stores bit 3 to 18 of the oui (00606e) to bit 15 to 0 of this register respectively. the m ost significant two bits of the oui are ignored (the ieee standard refers to these as bit 1 and 2) phy identifier register #2 (phyid2) - 03 bit bit name default description 3.15-3.10 oui_lsb <101110>, ro/p oui least significant bits: bit 19 to 24 of the oui (00606e) are mapped to bit 15 to 10 of this register respectively 3.9-3.4 vndr_mdl <000010>, ro/p vendor model number: six bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3.3-3.0 mdl_rev <0000>, ro/p model revision number: four bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 3)
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 15 version: DM9131-ds-f01 april 7, 2000 auto-negotiation advertisement register(anar) - 04 this register contains the advertised ab ilities of this DM9131 device as t hey will be transmitted to its link partner during auto-negotiation. bit bit name default description 4.15 np 0,ro/p next page indication: 0 = no next page available 1 = next page available the DM9131 has no next page, so this bit is perm anently set to 0 4.14 ack 0,ro acknowledge: 1 = link partner ability data reception acknowledged 0 = not acknowledged the DM9131's auto-negotiation state machine w ill automatically control this bit in the outgoing flp bu rsts and set it at the appropriate time during the auto-negotiation process. software should not attempt to write to this bit. 4.13 rf 0, rw remote fault: 1 = local device senses a fault condition 0 = no fault detected 4.12-4.11 reserved x, rw reserved: write as 0, ignore on read 4.10 fcs 0, rw flow control support: 1 = controller chip supports flow control ab ility 0 = controller chip doesn?t support flow control ab ility 4.9 t4 0, ro/p 100base-t4 support: 1 = 100base-t4 is supported by the local device 0 = 100base-t4 is not supported the DM9131 does not support 100base-t4 so this bit is permanently set to 0 4.8 tx_fdx 1, rw 100base-tx full duplex s upport: 1 = 100base-tx full duplex is supported by the local device 0 = 100base-tx full duplex is not supported 4.7 tx_hdx 1, rw 100base-tx support: 1 = 100base-tx is supported by the local device 0 = 100base-tx is not supported 4.6 10_fdx 1, rw 10base-t full duplex support: 1 = 10base-t full duplex is supported by the local device 0 = 10base-t full duplex is not supported 4.5 10_hdx 1, rw 10base-t support: 1 = 10base-t is supported by the local device 0 = 10base-t is not supported 4.4-4.0 selector <00001>, rw protocol selection bits: these bits contain the binary encoded protocol selector supported by this node. <00001> indicates that this device supports ieee 802.3 csma/cd.
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 16 final version: DM9131-ds-f01 april 7, 2000 auto-negotiation link partner ability register (anlpar) ? 05 this register contains the advertised ab ilities of the link partner when received during a uto- negotiation. bit bit name default description 5.15 np 0, ro next page indication: 0 = link partner, no next page available 1 = link partner, next page available 5.14 ack 0, ro acknowledge: 1 = link partner ability data reception acknowledged 0 = not acknowledged the DM9131's auto-negotiation state machine w ill automatically control this bit from the incoming flp bursts. software should not attempt to write to this bit. 5.13 rf 0, ro remote fault: 1 = remote fault indicated by link partner 0 = no remote fault indicated by link partner 5.12-5.11 reserved x, ro reserved: write as 0, ignore on read 5.10 fcs 0, rw flow control support: 1 = controller chip supports flow control ab ility by link partner 0 = controller chip doesn?t support flow control ab ility by link partner 5.9 t4 0, ro 100base-t4 support: 1 = 100base-t4 is supported by the link partner 0 = 100base-t4 is not supported by the link partner 5.8 tx_fdx 0, ro 100base-tx full duplex support: 1 = 100base-tx full duplex is supported by the link partner 0 = 100base-tx full duplex is not supported by the link partner 5.7 tx_hdx 0, ro 100base-tx support: 1 = 100base-tx half duplex is supported by the link partner 0 = 100base-tx half duplex is not supported by the link partner 5.6 10_fdx 0, ro 10base-t full duplex s upport: 1 = 10base-t full duplex is supported by the link partner 0 = 10base-t full duplex is not supported by the link partner 5.5 10_hdx 0, ro 10base-t support: 1 = 10base-t half duplex is supported by the link partner 0 = 10base-t half duplex is not supported by the link partner 5.4-5.0 selector <00000>, ro protocol selection bits: link partner?s binary encoded protocol selector
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 17 version: DM9131-ds-f01 april 7, 2000 auto-negotiation expansion register (aner)- 06 6.15-6.5 reserved x, ro reserved: write as 0, ignore on read 6.4 pdf 0, ro/lh local device parallel detection fault: pdf = 1 : a fault detected via parallel detection function. pdf = 0 : no fault detected via parallel detection function 6.3 lp_np_able 0, ro link partner next page able: lp_np_able = 1 : link partner, next page available lp_np_able = 0 : link partner, no next page 6.2 np_able 0,ro/p local device next page able: np_able = 1 : DM9131, next page available np_able = 0 : DM9131, no next page DM9131 does not support this function, so this bit is always 0. 6.1 page_rx 0, ro/lh new page received: a new link code word page received. this bit will be automati cally cleared when the register (register 6) is read by management. 6.0 lp_an_able 0, ro link partner auto-negotiation able: a ?1? in this bit indicates that the link partner supports auto- negotiation. davicom specified configuration register (dscr) - 16 bit bit name default description 16.15 bp_4b5b (pin#xx), rw bypass 4b5b en coding and 5b4b decoding : the value of the bp4b5b pin(xx) is latched into this bit at power- up/reset. 1 = 4b5b encoder and 5b4b decoder function bypassed 0 = normal 4b5b and 5b4b operation 16.14 bp_scr 0, rw bypass scrambler/descrambler function : 1 = scrambler and descrambler function bypassed 0 = normal scrambler and descrambler operation 16.13 bp_align 0, rw bypass sym bol alignment function: 1 = receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. transmit functions ( symbol encoder and scrambler) bypassed 0 = normal operation 16.12 bp_adpok 0, rw bypass adpok : force signal detector (sd) active. this register is for debug only, not release to customer. 1=force sd is ok, 0=normal operation 16.11 repeater (pin#xx),rw repeater/node mode : the value of the repeater/node pin(xx) is latched into this bit at power-up/reset. 1 = repeater mode 0 = node mode 16.10 tx 1, rw 100base-tx or fx mode control: 1 = 100base-tx operation 0 = 100base-fx operation
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 18 final version: DM9131-ds-f01 april 7, 2000 16.9 fef 0, rw far end fault enable : control the far end fault mechanism associated with 100base-fx operation. 1 = enable 0 = disable 16.8 rmii_enable (pin#xx), rw reduced mii enable : select normal mii or reduced m ii. the value of the rmii pin(xx) is latched into this bit at power-up/reset. 0 = normal mii 1 = enable reduced mii 16.7 f_link_100 0, rw force good link in 100mbps: 0 = normal 100mbps operation 1 = force 100mbps good link status this bit is useful for diagnostic purposes. 16.6 spled_ctl 0, rw speed led disable : 0 : normal speedled output to indicate speed status 1 : disable speedled output and enable sd signal monitor (for internal debug). when this bit is set, it control the speedled as 100base-x sd (not fiber mode) signal output .for debug only. 16.5 reserved 0, ro reserved 16.4 fdxled_ctl 0,rw full-duplex led mode select : 0 = fdxled output is configured to indicate full-duplex status 1 = colled output is configured to indicate the presence of collision activity operation. 16.3 smrst 0, rw reset state machine: when writes 1 to this bit, all state machines of phy w ill be reset. this bit is self-clear after reset is compl eted. 16.2 mfpsc 0, rw mf preamble suppression c ontrol: mii frame preamble suppression control bit 1 = mf preamble suppression bit on 0 = mf preamble suppression bit off 16.1 sleep 0, rw sleep mode: writing a 1 to this bit w ill cause phy entering the sleep mode and power down all circuit ex cept oscillator and clock generator circuit. when waking up from sleep mode (write this bit to 0), the configuration will go back to the s tate before sleep; but the state machine will be reset 16.0 rlout 0, rw remote loopout control: when this bit is set to 1, the received data w ill loop out to the transmit channel. this is useful for bit error rate testing
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 19 version: DM9131-ds-f01 april 7, 2000 davicom specified configuration and status register (dscsr) - 17 bit bit name default description 17.15 100fdx 1, ro 100m f ull dup lex operat ion mode: after auto-negotiation is completed, results w ill be written to this bit. if this bit is 1, it means the operation 1 mode is a 100m full duplex mode. the software can read bit[15:12] to see which m ode is selected after auto- negotiation. this bit is invalid w hen it is not in the auto- negotiat ion m ode. 17.14 100hdx 1, ro 100m half duplex operation mode: after auto-negotiation is completed, results w ill be written to this bit. if this bit is 1, it means the operation 1 mode is a 100m half duplex mode. the software can read bit[15:12] to see which m ode is selected after auto- negotiation. this bit is invalid w hen it is not in the auto- negotiat ion m ode. 17.13 10fdx 1, ro 10m full dup lex operat ion mode: after auto-negotiation is completed, results w ill be written to this bit. if this bit is 1, it means the operation 1 mode is a 10m full duplex mode. the software can read bit[15:12] to see which m ode is selected after auto- negotiation. this bit is invalid w hen it is not in the auto- negotiat ion m ode. 17.12 10hdx 1, ro 10m half duplex operation mode: after auto-negotiation is completed, results w ill be written to this bit. if this bit is 1, it means the operation 1 mode is a 10m half duplex mode. the software can read bit[15:12] to see which m ode is selected after auto- negotiation. this bit is invalid w hen it is not in the auto- negotiat ion m ode. 17.11- 17.9 reserved 0, ro reserved: write as 0, ignore on read 17.8-17.4 phyadr[4:0] (phyadr), rw phy address bit 4:0: the first phy address bit transmitted or received is the msb of the address (bit 4). a station management entity connected to m ultiple phy entities must know the appropriate address of each phy. 17.3-17.0 anmb[3:0] 0, ro auto-negotiation monitor bits: these bits are for debug only. the auto- negotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 in idle state 0 0 0 1 ability match 0 0 1 0 acknowledge match 0 0 1 1 acknowledge match fail 0 1 0 0 consistency match 0 1 0 1 consistency match fail 0 1 1 0 parallel detects signal_link_ready 0 1 1 1 parallel detects signal_link_ready fail 1 0 0 0 auto-negotiation completed successfully
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 20 final version: DM9131-ds-f01 april 7, 2000 10base-t configuration/status (10btcsr) - 18 bit bit name default description 18.15 reserved 0, ro reserved: write as 0, ignore on read 18.14 lp_en 1, rw link pulse enable: 1 = transmission of link pulses enabled 0 = link pulses disabled, good link c ondit ion forced this bit is valid only in 10mbps operation. 18.13 hbe 1,rw heartbeat enable: 1 = heartbeat function enabled 0 = heartbeat function disabled when the DM9131 is configured for full duplex operation, this bit will be ignored (the co llision/ heartbeat function is invalid in full duplex mode). 18.12 squelch 1, rw squelch enable : 1 = normal squelch 0 = low squelch 18.11 jaben 1, rw jabber enable: enables or disables the jabber function when the DM9131 is in 10base-t full duplex or 10base-t transceiver loopback mode 1 = jabber function enabled 0 = jabber function disabled 18.10 10bt_ser 0,rw 10base-t serial mode: 1 = 10base-t serial mode selected 0 = 10base-t nibble mode selected serial mode is not supported for 100mbps operation. 18.9-18.1 reserved 0, ro reserved: write as 0, ignore on read 18.0 polr 0, ro polarity reversed: when this bit is set to 1, it indicates that the 10mbps cable polarity is reversed. this bit is set and cleared by 10base-t module automatically.
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 21 version: DM9131-ds-f01 april 7, 2000 davicom specified interrupt register ? 21 bit bit name default description 21.15 intr pend 0, ro interrupt pending : indicates that the interrupt is pending and is c leared by the current read. this bit shows the same result as bit 0. (intr status) 21.14- 21.12 reserved 0, ro reserved 21.11 fdx mask 1, rw full-duplex interrupt mask : when this bit is set, the duplex status c hange w ill not generate the interrupt 21.10 spd mask 1, rw speed interrupt mask : when this bit is set, the speed status change w ill not generate the interrupt 21.9 link mask 1, rw link interrupt mask : when this bit is set, the link status change w ill not generate the interrupt 21.8 intr mask 1, rw master interrupt mask : when this bit is set, no interrupts w ill be generated under any condition. 21.7-21.5 reserved 0, ro reserved 21.4 fdx change 0,ro/lh duplex status change interrupt : ?1? indicates a change of duplex since last register read. a read of this register will clear this bit. 21.3 spd change 0, ro/lh speed status change interrupt : ?1? indicates a change of speed s ince last register read. a read of this register will clear this bit. 21.2 link change 0, ro/lh link status change interrupt : ?1? indicates a change of link since last register read. a read of this register will clear this bit. 21.1 intr enable 0, rw interrupt enable : ?1? = enable the interrupt mode, ?0? = disable 21.0 intr status 0, ro/lh interrupt status : the status of mdintr# . ?1? indicates that the interrupt mask is off that one or more of the c hange bits are s et. a read of this register will clear this bit. davicom specified receive error c ounter register (recr) ? 22 bit bit name default description 22.15-0 rcv_err_cnt 0, ro receive error counter : receive error counter that inc rements upon detection of reer davicom specified disconnect counter register (discr) ? 23 bit bit name default description 23.15- 23.8 reserved 0, ro reserved 23.7-23.0 disconnect counter 0, ro disconnect counter that increments upon detection of disconnection.
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 22 final version: DM9131-ds-f01 april 7, 2000 absolute maximum ratings absolute maximum ratings ( 25 c ) symbol parameter min. max. unit conditions d vcc, a vcc supply voltage -0.3 3.6 v v in dc input voltage (v in )-0.55.5v v out dc output voltage(v out )-0.33.6v t stg storage temperature rang (t stg ) -40 +125 c p d power dissipation (p d ) --- 0.43 w l t lead temp. (t l , soldering, 10 sec.) --- 240 c operating conditions symbol parameter min. max. unit conditions d vcc ,a vcc supply voltage 3.135 3.465 v tc case temperature --- 85 c 100base-tx --- 115 m a 3.3v 100base-fx --- 25 m a 3.3v 10base-t tx --- 125 m a 3.3v 10base-t idle --- 44 m a 3.3v p d (power dissipation) auto-negotiation --- 76 m a 3.3v comments stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 23 version: DM9131-ds-f01 april 7, 2000 dc electrical characteristics (vcc = 3.3v) symbol parameter min. typ. max. unit conditions ttl inputs (txd0~txd3, txclk, mdc, mdio, txen, txer, rxen, testmode, rmii, oscsel, phyad0~4, opmode0-2, rptr, bp4b5b, reset# ) v il input low voltage --- --- 0.8 v v ih input high voltage 2.0 --- --- v i il input low leakage current --- --- 10 u a v in = 0.4v i ih input high leakage current --- --- -10 u a v in = 2.7v mii ttl outputs ( rxd0-rxd3, rxdv, rxer, crs, col, mdio) v ol output low voltage --- --- 0.4 v i ol = 4m a v oh output high voltage 2.4 --- --- v i oh = -4m a non-mii ttl outputs (linkled#, speedled#, fdxled#, mdintr#) v ol output low voltage --- --- 0.4 v i ol = 1m a v oh output high voltage 2.4 --- --- v i oh = -0.1m a receiver v icm rx+/rx- common mode input voltage --- 0.9 --- v 100 ? termination across transmitter v td 100 100tx+/- differential output voltage 1.9 2.0 2.1 v peak to peak v td 10 10tx+/- differential output voltage 4.4 5 5.6 v peak to peak i td 100 100tx+/- differential output current 19 20 21 m a i td 10 10tx+/- differential output current 44 50 19 m a v oh pecl output voltage ? high v cc- 1.05 v cc - 0.88 v v ol pecl output voltage ? low v cc- 1.81 v cc- 1.62 v i fd 100 100fx+/- differential output current 17 18 19 m a ac electrical characteristics & timing waveforms tp interface symbol parameter min. typ. max. unit conditions t tr/f 100tx+/- differential rise/fall time 3.0 --- 5.0 ns t tm 100tx+/- differential rise/fall time mismatch 0 --- 0.5 ns t tdc 100tx+/- differential output duty cycle distortion 0 --- 0.5 ns t t/t 100tx+/- differential output peak-to-peak jitter 0 --- 1.4 ns xost 100tx+/- differential voltage overshoot 0 --- 5 % oscillator/crystal timing symbol parameter min. typ. max. unit conditions t ckc osc cycle time 39.998 40 40.002 ns 50ppm t pwh osc pulse width high 16 20 24 ns t pwl osc pulse width low 16 20 24 ns
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 24 final version: DM9131-ds-f01 april 7, 2000 mdc/mdio timing symbol parameter min. typ. max. unit conditions t 0 mdc cycle time 80 --- --- ns t 1 mdio setup before mdc 10 --- --- ns when output by sta t 2 mdio hold after mdc 10 --- --- ns when output by sta t 3 mdc to mdio output delay 0 --- 300 ns when output by DM9131 mdio timing when output by sta mdc t 1 mdio 10ns (min) t 2 10ns (min) t0 mdio timing when output by DM9131 mdc t 3 mdio 0 - 300 ns
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 25 version: DM9131-ds-f01 april 7, 2000 100base-tx transmit timing parameters symbol parameter min. typ. max. unit conditions t txc txclk cycle time 39.996 40 40.004 ns t txh , t txl txclk high/low time 16 20 24 ns t tx s txd[0:3], txen, txer setup to txclk high 15 --- --- ns t tx h txd[0:3], txen, txer hold from txclk high 15 --- --- ns t txod txclk to output delay 25 ns t 1 txen sampled to crs asserted --- 4 --- bt t 2 txen sampled to crs de-asserted --- 4 --- bt t tx pd txen sampled to tx+/- out(tx latency) --- 8 --- bt t tx r/f 100tx driver rise/fall time 3 4 5 ns 90% to 10%, into 100ohm differential 1 . typical values are at 25 and are for design aid only; not guaranteed and not subject to production t esting. 100base-tx transmit timing diagram txclk t tx h t 2 t tx s t 1 t tx pd t tx r/f txd [0:3], txen, txer crs 100tx+/- ttxc ttxh ttxod 100base-tx receive timing parameter symbol parameter min. typ. max. unit conditions t rxc rxclk cycle time 39.996 40 40.004 t rxh, t rxl rxclk high/low time 16 20 24 t rx s rxd[0:3), rxdv, rxer setup to rxclk high 10 - - ns t rx h rxd[0:3], rxdv, rxer hold from rxclk high 10 - - ns t rx pd rx+/- in to rxd[0:3] out (rx latency) - 15 - bt t 1 crs asserted to rx d[0:3], rxdv, rxer - 4 - bt t 2 crs de-asserted to rxd[0:3], rxdv, rxer - 0 - bt t 3 rx+/- in to crs asserted 10 - 14 bt t 4 rx+/- quiet to crs de-asserted 14 - 18 bt t 5 rx+/- in to col de-asserted 14 - 18 bt 1 . typical values are at 25 and are for design aid only; not guaranteed and not subject to production t esting.
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 26 final version: DM9131-ds-f01 april 7, 2000 mii 100base-tx receive timing diagram rxclk t 2 t 1 t tx pd rxd [0:3], rxdv, rxer crs rx+/- t rx s t rx h t 4 t 3 col t 5 t 5 trxc trxh mii 10base-t nibble transmit timing parameters symbol parameter min. typ. max. unit conditions t tx s txd[0:3), txen, txer setup to txclk high 5 --- --- ns t tx h txd[0:3], txen, txer hold from txclk high 5 --- --- ns t 1 txen sampled to crs asserted --- 2 4 bt t 2 txen sampled to crs de-asserted --- 15 20 bt t tx pd txen sampled to 10txo out (tx latency) --- 2 4 bt mii 10base-t nibble transmit timing diagram txclk t tx h t 2 t tx s t 1 t tx pd txd [0:3], txen, txer crs 10tx+/-
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 27 version: DM9131-ds-f01 april 7, 2000 mii 10base-t receive nibble timing parameters symbol parameter min. typ. max. unit conditions t rx s rxd[0:3), rxdv, rxer setup to rxclk high 5 --- --- ns t rx h rxd[0:3], rxdv, rxer hold from rxclk high 5 --- --- ns t rx pd rxi in to rxd[0:3] out (rx latency) --- 7 --- bt t 1 crs asserted to rx d[0:3], rxdv, rxer 1 14 20 bt t 2 crs de-asserted to rxd[0:3], rxdv, rxer --- --- 3 bt t 3 rxi in to crs asserted 1 2 4 bt t 4 rxi quiet to crs de-asserted 1 10 15 bt mii 10base-t receive nibble timing diagram rxclk t 2 t 1 t tx pd rxd [0:3], rxdv, rxer crs rx+/- t rx s t rx h t 4 t 3 auto-negotiation and fast link pulse timing parameters symbol parameter min. typ. max. unit conditions t 1 clock/data pulse width --- 100 --- ns t 2 clock pulse to data pulse period 55.5 62.5 69.5 us data = 1 t 3 clock pulse to clock pulse period 111 125 139 us t 4 flp burst width - 2 - ms t 5 flp burst to flp burst period 8 24 ms - clock/data pulses in a burst 17 33 pulse
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 28 final version: DM9131-ds-f01 april 7, 2000 auto-negotiation and fast link pulse timing dia gram flp bursts t 3 flp burst flp burst t 4 t 5 nlps fast link pulses clock pulse data pulse clock pulse t 1 t 2 t 3 flp burst flp burst t 4 t 5 10tx0+/- t 1
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver final 29 version: DM9131-ds-f01 april 7, 2000 package information lqfp 100l outline dimensions unit: inches/mm

d y symbol dimensions in inches dimensions in mm a 0.063 max. 1.60 max. a 1 0.004 0.002 0.1 0.05 a 2 0.055 0.002 1.40 0.05 b0.009 0.002 0.22 0.05 c0.006 0.002 0.15 0.05 d 0.551 0.005 14.00 0.13 e 0.551 0.005 14.00 0.13 e 0.020 bsc. 0.50 bsc. f 0.481 nom. 12.22 nom. g d 0.606 nom. 15.40 nom. h d 0.630 0.006 16.00 0.15 h e 0.630 0.006 16.00 0.15 l 0.024 0.006 0.60 0.15 l 1 0.039 ref. 1.00 ref. y 0.004 max. 0.1 max. 0 ~ 12 0 ~ 12 note: 1. dimension d & e do not include resin fins. 2. dimension gd is for pc board surface mount pad pitch design reference only. 3. all dimensions are based on metric system.
DM9131 10/100 mbps fast ethernet physical layer single chip transceiver 30 final version: DM9131-ds-f01 april 7, 2000 ordering information part number pin count p ackage DM9131 100 lqfp disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by d avicom semiconductor are covered by the warranty and patent indemnification pro visions st ipulated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. davicom deserves the right to halt production or alter the spe cificat ions and prices at any time without notice. accordingly, the reader is cautioned to verify that the data s heets and other information in this publication are current before placing orders. pr oducts descri bed herein are intended for use in normal commer cial applications. applications involving unusual environmental or reliability requirements, e.g. m ilitary equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrated in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless d avicom agrees otherwise in w riting. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor, inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic products that re the industry?s best value for data, audio, video, and interne t/intr anet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while st ill delivering pr oducts that meet their cost requirements. products we offer only produ cts that satisfy high performance requirements and which are compatible with major hardware and software standards. our currently available and soon to be released pr oducts are ba sed on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom pr oducts, contact the sales department at: headquarters hsin-chu office: 3f, no. 7-2, industry e. rd., ix, science-based park, hsin-chu city, taiwan, r.o.c. tel: 886-3-5798797 fax: 886-3-5798858 taipei sales & marketing office: 8f, no. 3, lane 235, bao-chiao rd., hsin-tien, taipei, taiwan, r.o.c. tel: 02-29153030 fax: 02-29157575 email: sales@davicom.com.tw davicom usa sunnyvale, california 1135 kern ave., sunnyvale, ca94086, u.s.a. tel: 1-408-7368600 fax: 1-408-7368688 email: sales@davicom8.com warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limit s of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, perfor mance and/or function .

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